The present invention relates to complementary metal oxide semiconductor (CMOS) integrated circuits, and more particularly to three-dimensional CMOS integrated circuits having semiconductor device layers that are built on different crystal oriented wafers.
In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today""s semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2xc3x97-4xc3x97 lower than the corresponding electron hole mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2xc3x97 higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above discussion, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
It is becoming more difficult to achieve substantial integrated circuit (IC) performance enhancement by traditional CMOS device and interconnect scaling. New materials introduced into the front-end and back-end of IC fabrication are enabling the continuation of the performance trends, but such innovations may provide only a one-time or a short-lived boost, and fundamental physical limits may soon be reached.
There are several prior art techniques that are currently employed in fabricating 3D integrated circuits. In one prior art technique, the lowest device layer is fabricated on a bulk substrate or a silicon-on-insulator (SOI) substrate and then a second device layer is formed. The second device layer can be formed by epitaxial Si growth. Such a method is described, for example, in S. Pae, et al., xe2x80x9cMultiple layers of silicon-on-insulator island fabrication by selective epitaxial growth,xe2x80x9d IEEE Elec. Dev. Lett 20:196-196 (1999). Another prior art technique to form the second device layer is by recrystallization of an amorphous Si layer. This approach is described, for example, in V. Subramanian, et al. xe2x80x9cHigh performance Germanium seeded laterally crystallized TFTs for vertical device integrationxe2x80x9d, IEEE Trans. Electron Devices 45, 1934-1939 (1998); T. Kunio, et al. xe2x80x9cThree dimensional IC""s having four stacked active device layersxe2x80x9d, IEDM Tech Dig 837-840 (1989); and V. W. C. Chan, et al. xe2x80x9cThree-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallizationxe2x80x9d, IEEE Trans Elec Dev 48:1394-1399 (2001).
Subsequent processes can then be performed in such prior art techniques to fabricate additional active devices and interconnecting wiring. Circuits fabricated in this manner suffer from two main drawbacks: (1) the recrystallized top layer often has poor electrical properties and it may result in lower device and circuit performance; it is also difficult to control the surface orientation of the recrystallized layer; (2) the thermal cycling from the top layer formation and sequential device fabrication degrades underlying device performance.
In some prior art techniques, 3D integrated circuits are achieved by wafer bonding. The 3D integration scheme using wafer bonding is disclosed, for example, in R. J. Gutmann, et al. xe2x80x9cThree dimensional (3D) ICs: A technology platform for integrated systems and opportunities for new polmeric adhesivesxe2x80x9d Proc IEEE Int""l Conf on Polymers and Adhesives in Microelectronics and Photonics, Germany, 173-180 (2001); R. Reif, et al. xe2x80x9cFabrication technologies for three dimensional integrated circuitsxe2x80x9d Proc IEEE Int""l Symposium on Quality Electronic Design 33-37 (2002); and A. W. Topol, et al. A demonstration of wafer level layer transfer of high performance devices and circuits for three-dimensional integrated circuit fabricationxe2x80x9d Proc. AVS ICMI, 5-7 (2003).
Despite these current advances using 3D integration, there is no prior art that fabricates 3D integrated circuits having nFETs and pFETs which are built on different surface orientations. Hence, there is a need for providing a new and improved 3D integration scheme that allows for each type of device present on a semiconductor chip or wafer to be formed upon a crystallographic surface orientation that provides optimal performance for each specific device. For example, there is a need for providing a 3D integration scheme wherein all nFETs are built on a (100) crystallographic surface and all pFETs are built on a (110) crystallographic surface.
The present invention provides a three-dimensional (3D) integration scheme of fabricating a 3D integrated circuit in which the pFETs are located on a (110) crystallographic surface and the nFETs are located on a (100) crystallographic surface. The term xe2x80x9c3D integrated circuitxe2x80x9d can be defined as an IC that contains multiple layers of active devices with vertical interconnections between the layers. In a 3D IC, each transistor can access a greater number of nearest neighbors than in a conventional two-dimensional (2D) circuit, such that each transistor or functional block will have a higher bandwidth.
One advantage of 3D integration is increased packing density; by adding a third dimension to the conventional 2D layout, the transistor packing density can be improved thereby allowing a reduced chip footprint. This is particularly appealing for wireless or portable electronics. Another advantage of 3D integration is that the total interconnect lengths are shorten. This provides shorter interconnect delays, less noise and improved electro-migration reliability. A further benefit of 3D integration is that the overall chip performance at a given power consumption can be substantially improved over a conventional 2D IC.
In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate that is optimal for the first semiconductor devices and second semiconductor devices, which are different from the first semiconductor devices, are pre-built on a semiconductor surface of a second SOI substrate that is optimal for the second semiconductor devices. After pre-building those two structures, the structures are bonded together and interconnected through wafer-via through vias.
In broad terms, the first 3D integration scheme of the present invention comprises the steps of:
providing a first interconnect structure comprising at least a first semiconductor device located on a surface of a first Si-containing layer of a first silicon-on-insulator substrate, said first Si-containing layer having a first surface orientation that is optimal for said first semiconductor device;
attaching a handling wafer to a surface of the first interconnect structure;
providing a second interconnect structure comprising at least a second semiconductor device that differs from the first semiconductor device on a surface of a second Si-containing layer of a second silicon-on-insulator substrate, said second Si-containing layer having a second surface orientation that is optimal for said second semiconductor device;
bonding the first and second interconnect structures to each other; and
removing the handling wafer.
In some embodiments of the present 3D integration scheme, vertical interconnects are provided between the first and second semiconductor devices.
In addition to the first 3D integration scheme mentioned above, the present invention also provides a second 3D integration scheme. The second 3D integration scheme of the present invention comprises:
bonding a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation to a surface of a pre-fabricating wafer having at least one second semiconductor device on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and
forming at least one first semiconductor device in said first SOI layer.
In accordance with the present invention, the first semiconductor device may be a pFET and the first crystallographic orientation may be (110), while the second semiconductor device may be an nFET and the second crystallographic orientation may be (100). It is also possible in the present invention, that the first semiconductor device is an nFET and the first crystallographic orientation may be (100) and that the second semiconductor device is a pFET and the second crystallographic orientation maybe (110).
The present invention also provides a three dimensional (3D) integrated circuit that includes:
a first interconnect structure comprising at least a first semiconductor device located on a surface of a first Si-containing layer of a first silicon-on-insulator substrate, said first Si-containing layer having a first surface orientation that is optimal for said first semiconductor device;
a second interconnect structure comprising at least a second semiconductor device that differs from the first semiconductor device located on a surface of a second Si-containing layer of a second silicon-on-insulator substrate, said second Si-containing layer having a second surface orientation that is optimal for said second semiconductor device; and
vertical interconnects connecting the first interconnect structure to the second interconnect structure.